The present invention relates generally to electronic memory devices, and more particularly to arrays of non-volatile memory cells for use in electronic memory devices such as electrically erasable programmable read-only memories (EEPROMs).
A non-volatile memory device is capable of retaining stored information after disconnection of its power source. An EEPROM is a type of non-volatile memory device in which information is written to and erased from the memory cells thereof using an electrical signal. EEPROMs are often implemented as xe2x80x9cflashxe2x80x9d memory devices in which all memory cells or designated sectors of cells can be simultaneously erased. Such devices typically utilize floating gate transistor structures in which the floating gate used to store charge upon programming of the cell is formed from a single layer of polysilicon. These single-poly flash EEPROMs are particularly well suited for use in applications requiring embedded, low cost, medium density arrays of non-volatile memory cells, such as parameter, protocol, code and data storage for processors and other types of integrated circuits.
Examples of single-poly flash EEPROM memory cells known in the art are described in U.S. Pat. No. 6,191,980, issued Feb. 20, 2001 in the name of inventors P. J. Kelley et al. and entitled xe2x80x9cSingle-Poly Non-Volatile Memory Cell Having Low-Capacitance Erase Gate,xe2x80x9d R. J. McPartland et al., xe2x80x9cSRAM Embedded Memory with Low Cost, FLASH EEPROM-Switch-Controlled Redundancy,xe2x80x9d Proceedings of the IEEE Custom Integrated Circuits Conference, Orlando, Fla., May 21-24, 2000, pp. 287-289, and R. J. McPartland and R. Singh, xe2x80x9c1.25 Volt, Low Cost, Embedded FLASH Memory for Low Density Applications,xe2x80x9d Proceedings of the 2000 Symposium on VLSI Circuits, Honolulu, Hawaii, Jun. 15-17, 2000, pp. 158-161, all of which are incorporated by reference herein.
FIG. 1 shows a schematic diagram of a single-poly flash EEPROM memory cell 100 of the type described in the above-cited U.S. Pat. No. 6,191,980. The memory cell 100 includes a control device M1 in the form of a control gate capacitor, a switch device M2, and an erase device M3. M1 and M3 are implemented as P-type metal oxide semiconductor (PMOS) devices, and M2 is implemented as an N-type MOS (NMOS) device. The control device M1, switch device M2 and erase device M3 all share a common polysilicon floating gate 102 designed to retain charge after the cell is written, i.e., programmed.
Programming in the memory cell 100 is by hot electron injection and erasure is by Fowler-Nordheim (F-N) tunneling. In operation, the cell is written or programmed by applying a voltage of about 5 volts to control gate 104 while drain terminal 108 of M2 is about 5 volts and erase gate 106 and source terminal 10 of M2 are held at about 0 volts, and the cell is erased by applying a voltage of about 10 volts to erase gate 106 while control gate 104 and terminals 108 and 110 are held to about 0 volts.
The object of an erase operation is to raise the potential of the floating gate 102 such that when the floating gate is coupled to the control gate 104 during a subsequent read operation, the potential of the floating gate will be above the threshold of the switch device M2 and M2 will thereby be conductive. Tunneling of electrons from the floating gate 102 through the gate oxide layer of device M3 associated therewith to source/drain and N-well regions of device M3 raises the potential of the floating gate. In a program operation, the potential of the floating gate 102 is lowered by the above-noted hot electron injection such that when the floating gate is coupled to the control gate 104 during a subsequent read operation, the potential of the floating gate will be below the threshold of the switch device M2 and M2 will thereby be non-conductive.
FIG. 2 shows a topological view of the memory cell 100. The device 100 includes N-well regions 120 and 122 formed in a P-type substrate. Devices M1 and M3 are formed in the N-well regions 120 and 122, respectively, while device M2 is formed in an N-type source-drain implant region 124. P-type source-drain implant regions 126 and 128 are formed in the respective N-well regions 120 and 122. Thin oxide or xe2x80x9cthinoxxe2x80x9d regions 130 and 132 are associated with the respective devices M1 and M2, while thinox source/drain contact regions 134 and 136 are associated with the device M3. An additional thinox region 137 is present between the regions 134 and 136. Windows 131-1 and 131-2 are formed in the thinox region 130, and similar windows are formed in the thinox regions 132 and 134. Elements 140 and 142 associated with the respective N-well regions 120 and 122 are N-well ties each having a window formed therein. Element 144 is a P-well tie associated with the P-type substrate.
FIGS. 3A and 3B show respective topological and side sectional views of the erase device M3 in the conventional memory cell 100. The FIG. 3B sectional view is taken along the line Bxe2x80x94Bxe2x80x2 shown in FIG. 3A. It can be seen from FIG. 3A that the floating gate 102 overlies the thinox region 137. The N-well tie 142 of FIG. 3A is formned in a P-type substrate 160 and corresponds to a region 162 in the N-well 122. Source/drain contact regions 134 and 136 correspond to source/drain regions 164 and 166 in the N-well 122. As is apparent from the schematic diagram of FIG. 1, both the source/drain regions 164, 166 and the N-well tie region 162 are electrically connected together to form one terminal (i.e., erase gate 106) of the erase device M3. The other terminal of the erase device M3 is the floating gate 102. The erase operation in the memory cell 100 involves tunneling of electrons from the floating gate 102 to the source/drain and N-well tie regions, via the above-noted F-N tunneling effect.
A potential drawback of the memory cell 100 is the amount of circuit area required to implement the erase device M3. More particularly, the erase device M3 of the memory cell 100 as illustrated in FIGS. 3A and 3B includes the N-well tie region 162 and two source/drain regions 164, 166, which collectively occupy a substantial amount of area within the memory cell 100. In addition, when multiple memory cells of this type are combined into a memory cell array, the erase device M3 is replicated in fail for each of the memory cells, further increasing the area requirements. For example, an array of eight non-volatile memory cells would conventionally require eight separate erase devices having a total of sixteen source/drain contacts and eight N-well tie contacts. However, in order to minimize fabrication costs for the corresponding memory device, it is desirable to reduce the memory cell area. A need therefore exists in the art for a non-volatile memory cell and associated cell array having an erase device structure which requires less area than the conventional arrangements previously described.
The present invention overcomes the above-described drawback of the prior art by providing a non-volatile memory device in which an array of memory cells share an erase device.
In accordance with one aspect of the invention, a non-volatile memory device includes an erase device that is shared among an array of memory cells. Each of the memory cells includes a control device coupled to a switch device via a common floating gate. Each of at least a subset of the memory cells further includes a portion of the shared erase device, the portion of the shared erase device associated with a given one of the memory cells being coupled to the switch device of that cell via the floating gate of that cell. The shared erase device is utilizable in performing an erase operation for each of the memory cells associated therewith.
In an illustrative embodiment of the invention, a non-volatile memory cell array includes eight memory cells, and the shared erase device is configured so as to be shared among the eight memory cells. More particularly, the eight memory cells may be configured in two groups of four cells each, with the shared erase device being arranged in a region of the device between the two groups of cells, and the floating gates associated with each of the cells extending into the region and forming elements of the shared erase device. Thus, in accordance with the techniques of the invention, an array of eight non-volatile memory cells which would conventionally require eight separate erase devices having a total of sixteen source/drain contacts and eight N-well tie contacts is instead configured to utilize a single shared erase device having only two source/drain contacts and one N-well tie contact.
Advantageously, the shared erase device structure of the present invention substantially reduces the area required to implement a memory device comprising one or more arrays of non-volatile memory cells. By way of example, a memory cell array fabricated in accordance with the above-noted illustrative embodiment of the invention has a memory cell size of 1.28 xcexcmxc3x9710.56 xcexcm (13.5 xcexcm2), representing a cell area reduction of about 80% relative to a conventional memory cell.
The invention is particularly well suited for implementation in single-poly flash EEPROM embedded memory devices in integrated circuit applications, but can also be used in other applications.